About the role - you will:

• Receive training on Functional Verification Methodologies at IP and SoC level using
• System Verilog and UVM
• Be able to work on verifying designs using Synopsys Simulation tools
• Develop Test-bench & Reference models in IP & SoC level verification environments
• Document and Implement Verification Plans
• Work closely with design engineers to create constrained random based test-benches and
• test cases to meet the required functional and code coverage metrics
• Debug and help resolve test failures
• Create reusable verification environments to be used across multiple teams
• Complete internship project as per plan

About you:

• Knowledge of ASIC design flow and tools
• Good understanding of Circuit design, Logic design, Setup time, Hold time, Combinatorial
• and Sequential circuits, CMOS and Power consumption
• Self-motivated & a strong team player
• Strong debug and analytical skills
• Ability to quickly learn new tools and technologies

Your experience includes:

• Knowledge of Verilog, SystemVerilog, VHDL, UVM or other verification methodologies
• Knowledge of C++ or other OOP languages with strong background in OOP concepts
• Perl, Tcl, Shell or other scripting languages
• Understanding of VLSI engineering cycle

Location:

Pune, India
Our site in Pune is dynamic, both in our cutting-edge, innovative work, as well as our vibrant on-site food, and athletic and personal development opportunities for our 400+ employees. You can enjoy breakfast, lunch, or dinner from one of four cafeterias in the park. Take a break from your workday and participate in one of our many walkathons or compete against your colleagues in carrom, chess and table tennis. Learn about a technical topic outside your area of expertise at one of our monthly Technical Speaker Series, or attend one of the frequent on-site cultural festivals, celebrations, and community volunteer opportunities.