The candidate will be responsible for developing validation infrastructure for testing SOC Firmware in emulation environment. This involves working with HW engineers, porting different SOC designs to emulation. Candidate will also be responsible for enabling different Bus Functional Models needed for emulation testing, developing necessary infrastructure for connecting emulators to Virtual Platforms. Candidate will also be required to enable FW validation in emulation, developing emulation test automation infrastructure for test execution.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Candidate should possess a Bachelor of Science degree or a Master of Science degree in Computer Science, Computer Engineering or Electrical Engineering.

Minimum requirements:

0-2+ years of emulation experience

Understanding of hardware modeling

C/C++ programming skills and/or Python scripting skills

Familiar with System Verilog or hardware description language (Verilog)


Preferred Requirements:

Experience related to SOC modeling in emulation

Experience with CPU, PCIe, DDR memory sub system

Experience with System Verilog programming

Understanding of SOC architectures