At Synopsys, we are Powering new era of innovation for high-performance silicon chips and exponentially growing amounts of software content. Synopsys is at the forefront of Smart Everything with the world’s most advanced technologies for chip design, verification, IP integration, and software security and quality testing. We help our customers innovate from silicon to software so they can bring amazing new products to life.
 
The candidate will be part of the Solutions Group, Bangalore, India. The position offers learning and growth opportunities. This is a Technical Intern role and offers challenges to work in a multi-site environment on technically challenging Design for IP Cores.
 
Selected candidate will be part of the DesignWare IP Design R&D team at Synopsys. He/She will be expected to specify, design/architect and implement FE RTL Design for the DesignWare family of synthesizable cores and perform quality checks for the deliverables.
 
Job role will have a combination of RTL quality verification by CDC/Lint check tools. Candidate will work closely with FE Verification Team and be part of a global team of experienced ASIC RTL Design Engineers.

Qualifications:

• BTech / MTech In Electrical / Electronic engineering 

Desirable Skills:

• Strong knowledge in Processor architecture and ASIC Design flow,
• HDL Verilog/VHDL/SV,
• Verification and Synthesis basics,
• Knowledge of perl or/and python is plus,
• Good communication skill,
• Good debug and problem-solving skills.